Output drivers are typically used, in part, to ensure that the generated output voltages stay within predefined limits. FIG. 1 is a transistor schematic diagram of a differential CMOS output driver 10, as known in the prior art. If input voltage Vin applied to the gate terminal of transistor 16 is greater than voltage Vip applied to the gate terminal of transistor 18, transistor 16 is on and transistor 18 is off. Therefore, node A is pulled to a relatively lower voltage, and node B is pulled to a relatively higher voltage. Therefore voltage signal Vop generated at the source terminal of transistor 20 is pulled to a relatively lower voltage, and voltage signal Von generated at the source terminal of transistor 22 is pulled to a relatively higher voltage. Similarly, if input voltage Vin is lower than voltage Vip, transistor 16 is off and transistor 18 is on. Therefore, node B is pulled to a relatively lower voltage, and node A is pulled to a relatively higher voltage. Therefore voltage signal Von is pulled to a relatively lower voltage, and voltage signal Vop is pulled to a relatively higher voltage.
Differential output driver 10 is adapted so as to maintain signals Von and Vop within the predefined voltage ranges VOH and VOL, as shown in FIG. 2. In other words, following a high-to-low transition by signal Von and a corresponding low-to-high transition by signal Vop, signal Von is maintained within the predefined limits of VOL, and signal Vop is maintained within the predefined limits of VOH. Similarly, following a high-to-low by signal Vop and a corresponding low-to-high transition by signal Von, signal Vop is maintained within the predefined limits of VOH, and signal Vop is maintained within the predefined limits of VOL, as shown in FIG. 2.
One known standard for differential output driver is referred to as the low voltage positive emitter coupled logic (LvPECL) standard, defined in JEDEC standard JESD8-2. This standard requires that VOH and VOL be within the following limits of supply voltage VDD:
MinMaxVOHVDD - 1.02 vVDD - 0.88 vVOLVDD - 1.81 vVDD - 1.62 v
The temperature and process induced variations in the gate-to-source and threshold voltages of the MOS transistors used in conventional CMOS output driver 10 render this output driver unable to meet the requirements defined by the LvPECL standard. Accordingly, a need continues to exist for a CMOS output driver adapted to meet the requirements defined by the LvPECL standard.